This invention generally relates to a framing algorithm for a bit interleaved time division multiplexer (TDM), and more particularly to as efficiency maximizing framing algorithm for a bit interleaved TDM which is compatible with a digital access cross-connect system (DACS).
The process of "framing", as known to those skilled in the art, is the process or mechanism of multiplexing a number of channels of varied rates onto a single aggregate line with proportional time allocation. The task undertaken by the framing mechanism is the time division and programming for a "framing RAM" hardware such that the hardware can continuously and periodically repeat a set of instructions. For example, if three channels having rates of 1200, 2400, and 4800 baud are to be multiplexed onto an aggregate line of 9600 baud, in accord with techniques known in the art, a common factor between the channel rates (the least common denominator) may be found, and this common factor will determine the length of the frame (or "frame length"). In the provided example, the common factor would be 1200, as each channel is divisable by that number. Thus, the 9600 aggregate line would have eight slots (9600/1200): one slot (1200/1200) being occupied by the 1200 baud channel; two slots (2400/1200) by the 2400 baud channel; and four (4800/1200) slots by the 4800 baud channel. The extra slot could be used for various purposes such as null data, synchonization, etc.
If additional channels having baud rates of 75 and 400 were added to the stated example, the aggregate line could accommodate them, as 1200 baud was unused. However, it will be appreciated that the least common denominator instead of being 1200, would drop to 25. Thus, the 9600 aggregate would be divided into 384 slots (i.e. 9600/25) as opposed to original 8 slots.
In reality, aggregates as high as 2.048MHz are common, with least common denominators of 25 Hz being common. As a result, a frame could have 81,920 slots with the same number of associated words being located in the frame RAM. Clearly, such a large memory would be disadvantageous both from an economic and a processing viewpoint. In response to this problem, a mechanism of repeating and "non-repeating" (also known as frames and superframes, or subframe and frames) which is discussed in commonly-owned U.S. Pat. No. 4,727,536 has been set forth to keep the frame length down. Thus, in the above-provided example, a repeating frame rate of 600 Hz could be utilized so that the frame would have sixteen slots (9600/600) while a superframe of 25 Hz could be utilized to muliplex the 75 Hz and 400 Hz channels onto the 600 Hz repeating frame. The superframe would have twenty-four slots, for a total of forty RAM frame words instead of the 384 previously required.
While the previously provided techniques have proved advantageous, there still exists an uncertainty as to selecting the repeating frame rate. For instance, while 600 Hz was chosen in the above example, it is possible that 800 or 1200 Hz would have been a better rate, at least in terms of minimizing frame RAM length. Moreover, in many framing algorithms of the art, where an attempt at framing fails due to the unavailability of enough RAM, the lowest rate channel is deleted and another framing is attempted. However, as will be appreciated by those skilled in the art after review of the instant disclosure, it is possible that by including a plurality of subframes (e.g. secondary and tertiary frames), and by optimizing the frame rates, that a given circumstance which would have given rise to a framing failure, can be accommodated.